| 6:00 - 8:00pm Registration |
| 7:30am - 5:00pm Registration |
| 7:30 - 8:20am Continental Breakfast |
| 8:20 - 8:30am Welcome Address |
Session 1: SOC Verification Methodologies
8:30 - 9:45am |
Session Chair: Priyadarsan Patra - Intel
- Positioning Test-Benches and Test-Programs in Interaction-Oriented System-on-Chip Verification
Xiaoxi Xu, Cheng-Chew Lim and Michael Liebelt - Univ. of Adelaide, Australia
- A Method for Hunting Bugs that Occur Due to System Conflicts
Daniel Geist and Oded Vaida - Intel Corp., Haifa, Israel
- Applications of Observer and Decorator Design Patterns in SoC Verification
Farzin Karimi - Metronome, Inc.
|
| 9:45 - 10:00am Break |
Session 2: Test
10:00 - 10:50am |
- A BIST Scheme for Full Characterization of ADC Parameters in Mixed-Signal SoCs
Chao Yuan, Yuanfu Zhao and Jun Du - Beijing Microelectronics Technology Institute
- Test Slice Difference Technique for Low Power Encoding
Wei-Lin Li, Tsung- Tang Chen, Po-Han Wu and Jiann-Chyi Rau-Tamkang Univ., Taiwan R.O.C.
|
| 10:50 - 11:00am Break |
Session 3: Panel - Software Practices for Verification/ Testbench Management
11:00am - 12:30pm |
Moderator: Shireesh Verma - Conexant Systems, Inc.
Panelists:
Mark Glassar - Mentor Graphics, Inc.
Badri Gopalan - Synopsys, Inc.
Srinath Atluri - Cisco Systems, Inc.
Sharon Rosenberg - Cadence Design Systems
Valeria Bertacco - Univ. of Michigan
|
| 12:30 - 2:00pm Lunch |
Session 4: Formal Verification
2:00 - 3:40pm |
Session Chair: Miroslav Velev - Aries Design Automation
- On Dynamic Switching of Navigation for Semi-Formal Design
Ankur Parikh and Michael Hsiao - Virginia Tech., USA
- Multi-Level Bounded Model Checking to Detect Bugs Beyond the Bound
Tasuku Nishihara, Takeshi Matsumoto and Masahiro Fujita - Univ. of Tokyo
- Proving and Disproving Assertion Rewrite Rules by Automated Theorem Proving
Katell Morin-Allory - TIMA, France, Marc Boulé - McGill Univ., Canada
Dominique Borrione - TIMA, France, Zeljko Zilic - McGill Univ., Canada
- Janus: A Novel Use of Formal Verification to do Targeted Behavioral Equivalence
Prakash Math and David Hoenig - Intel Corp., Hillsboro, OR, USA
|
| 3:40 - 3:55pm Break |
Session 5: Invited Session: On-Chip Instrumentation for Silicon Validation and Debug
3:55 - 5:55pm |
Session Chair: Jai Kumar - Sun
- In-System Silicon Validation Using a Reconfigurable Platform
Miron Abramovici - DAFCA
- On-Chip Instrument Application to SoC Analysis
Neal Stollon - HDL Dynamics, Inc.
|
Banquet Dinner and Keynote Address:
7:00 - 10:00pm |
| Keynote Speaker: TBD |
| 7:00am - 12:30pm Registration |
| 7:00 - 8:00am Continental Breakfast |
Session 6: Functional Testing and Verification
8:00 - 9:40am |
Session Chair: Eric Hennenhoefer - Obsidian Software
- Test and Validation of a Non-Deterministic System - True Random Number Generator
Kapila Udawatta, Sergey Maidanov, Mehdi Ehsanian and Surya Musunuri - Intel Corp.
- Functional Testing Approaches for BIFST-able tlm_fifo
Homa Alemzadeh - Univ. of Tehran, Iran
Stefano Di Carlo, Alberto Scionti and Paolo Prinetto - Politecnico de Torino, Italy
Zainalabedin Navabi - Univ. of Tehran, Iran
- IBM System z Functional and Performance Verification Using X-Gen
Torsten Schober, Shimon Landa, Bodo Hoppe and Ronny Morad - IBM Corp.
- Timing Verification of Distributed Network Systems at Higher Levels of Abstraction
Hassan Hatefi-Ardakani, Amir Masoud Gharehbaghi and Shaahin Hessabi - Sharif Univ. of Technology, Tehran
|
| 9:40 - 9:50am Break |
Session 7: Simulation
9:50 - 11:05am |
Session Chair: Mehdi Mohtashemi - Synopsys
- Temporal Parallel Gate-level Timing Simulation
Dusung Kim and Maciej Ciesielski - Univ. of Massachusetts, Amherst
Kyuho Shim and Seiyang Yang - Pusan National Univ., Korea
- The Role of Parallel Simulation on Functional Verification
Giuseppe Di Guglielmo, Franco Fummi - Univ. of Verona, Italy
Mark Hampton - Certess, France
Graziano Pravadelli and Francesco Stefanni - Univ. of Ve rona, Italy
- A HW/SW Co-Simulation Framework for the Verification of Multi-CPU Systems
Stefano Cordibella, Franco Fummi, Giovanni Perbellini and Davide Quaglia - Univ. of Verona, Italy
|
| 11:05 - 11:15am Break |
Session 8: Panel - SoC Power Management Implications on Validation and Testing
11:15am - 12:35pm |
Moderator: Bhanu Kapoor - Mimasic
Panelists:
John Goodenough - ARM
Manuel A d'Abreu - Sandisk Corp.
Shireesh Ve rma - Conexant Systems, Inc.
Kaushik Roy - Purdue Univ.
Shankar Hemmady - Synopsys, Inc. |
| 12:35 - 2:00pm Lunch |
Session 9: Special Session: What's So Intelligent about Testbenches?
2:00 - 3:30pm |
Organizer: Avi Ziv - IBM Corp.
- Automatic Test Generation for Coverage Improvement
Chris Wilson - Nusym Technology, Inc.
- Capturing Functional Intent in Intelligent Testbenches
Adnan Hamid - Breker Verification Systems
- Why Intelligent Verification Needs Functional Qualification
Joerg Grosse - Certess
|
| 3:30 - 3:40pm Break |
Session 10: Coverage and Metrics
3:40 - 4:30pm |
Session Chair: Rick Zucker - Intel
- Optimized Coverage-Directed Random Simulation
Inigo Ugarte and Pablo Sanchez - Univ. of Cantabria, Spain
- Evaluation of an Efficient Control-Oriented Coverage Metric
Kiran Ramineni, Shireesh Verma and Ian Harris - Univ. of California, Irvine
|
| 4:30 - 4:40pm Break |
Session 11: Defect and Fault Models and Test
4:40 - 5:55pm |
Session Chair: Seiyang Yang - Pusan National University
- High-Level Vulnerability over Space and Time to Insidious Soft Errors
Kenneth Zick and John Hayes - Univ. of Michigan
- Automating Defects Simulation and Fault Modeling for SRAMs
Stefano Di Carlo, Paolo Prinetto and Alberto Scionti - Politecnico de Torino, Italy
Zaid Al-Ars - Delft Univ. of Technology, The Netherlands
- Injecting Intermittent Faults for the Dependability Validation of Commercial Microcontrollers
Daniel Gil, Luis J. Saiz, Joaquin Gracia, Juan C. Baraza and Pedro Gil - Univ. Politecnica de Valencia, Spain
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