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PDF Version (Includes workshop and hotel registration forms)
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Registration - 5:00PM-7:30PM
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Buffet Reception - 7:30PM-9:30PM
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Session 1 - Formal Techniques - 8:10AM-9:50AM
- Enhancing Sequential Depth Computation with a Branch-and-Bound Algorithm
Chia-Chih Yen, Jing-Yang Jou - National Chiao-Tung University
- Reference Model Based RTL Verification: An Integrated Approach
William N. N. Hung and Naren Narasimhan - Intel Corporation
- Dynamic Guiding of Bounded Property Checking
Prakash M. Peranandam, Roland J. Weiss, Juergen Ruf, Thomas Kropf, Wolfgang Rosenstiel - University of T¨ubingen
- Towards an Efficient Assertion Based Verification of SystemC Designs
Ali Habibi and Sofiene Tahar - Concordia University
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Break - 9:50AM - 10:20AM
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Session 2 - Proccessor-Oriented Validation - 10:20AM-12:00PM
- TIS: An Instruction Level Test Methodology for CPU Core Software-Based Self-Testing
Saeed Shamshiri, Hadi Esmaeilzadeh and Zainalabedin Navabi - University of Tehran
- Simplifying Design and Verification for Structural Hazards and Datapaths in Pipelined Circuits
Jason T. Higgins - LSI Logic and Mark D. Aagaard - University of Waterloo
- ATPG Based Functional Test for Data Paths: Application to a Floating Point Unit
Ismet Bayraktaroglu, Manuel d'Abreu - Sun Microsystems
- Formal Verification of Pipelined Processors with Load-Value Prediction
Miroslav Velev - Resevior Labs
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Lunch - 12:00PM - 1:20PM
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Session 3 - Decision Diagrams for Verification - 1:20PM - 2:35PM
- On Using A 2-domain Partitioned OBDD Data Structure in Verification
Tao Feng, Li-C.Wang, Kwang-Ting Cheng - University of California Santa Barbara, Andy Lin - Cadence Design Systems
- Variable Ordering for Taylor Expansion Diagrams,"Daniel Gomez-Prado
Maciej Ciesielski, - University of Massachusetts Amherst, Emmanuel Boutillon - Université de Bretagne Sud
- MODD for CF: A Compact Representation for Multiple Output Function
Rajaprabhu T. L., Ashutosh K. Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan - University of Bristol
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Break - 2:35PM - 3:00PM
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Session 4 - Validation Pattern Generation - 3:00PM-4:15PM
- Functional Verification based on the EFSM Model
Franco Fummi, Cristina Marconcini, Graziano Pravadelli - Universit `a di Verona
- Enhancing Efficiency of Bayesian Network based Coverage Directed Test Generation
Markus Braun - STZ Softwaretechnik, Shai Fine, Avi Ziv - IBM Haifa
- Mutation-Based Validation of High-Level Microprocessor Implementations
Jorge Campos and Hussain Al-Asaad - University of California Davis
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Break - 4:15PM - 4:45PM
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Session 5 - Behavioral Modeling - 4:45PM - 6:00 PM
- Effects of Property Ordering in an Incremental Formal Modeling Methodology
Syed Suhaib, Deepak Mathaikutty, and Sandeep Shukla - Virginia Polytechnic Institute
- Efficient Test-based Model Generation for Legacy Reactive Systems
Tiziana Margaria - University of Gottingen, Oliver Niese - empolis GmbH, Harald Raffelt - University of Dortmund, Bernhard Steffen - University of Dortmund and METAFrame Technologies GmbH
- Model Validation for Mapping Specification Behaviors to Processing Elements
Samar Abdi and Daniel Gajski - University of California Irvine
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Session 6 - Fault Coverage Analysis - 8:00AM - 9:15AM
- Test Quality for High Level Structural Test
Edward McCluskey - Stanford University and Ahmad Al-Yamani - LSI Logic
- On Code Coverage Measurement for Verilog-A
Yuan-Bin Sha, Mu-Shun Lee and Chien-Nan Jimmy Liu - National Central University, Taiwan
- On Identifying Functionally Untestable Transition Faults
Xiao Liu and Michael S. Hsiao - Virginia Tech
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Break - 9:15AM - 9:35AM
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Session 7 - SAT Solving Approaches - 9:35AM - 10:50AM
- CNF Formula Simplification Using Implication Reasoning
Rajat Arora - Cadence Design Systems, Michael S. Hsiao - Virginia Tech
- Dynamic Analysis of Constraint-Variable Dependencies to Guide SAT Diagnosis
Vijay Durairaj and Priyank Kalla - University of Utah, Salt Lake City
- Exploiting Hypergraph Partitioning for Efficient Boolean Satisfiability
Vijay Durairaj and Priyank Kalla - University of Utah, Salt Lake City
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Break - 10:50AM - 11:10AM
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Session 8 - Validation of Network Architectures - 11:10AM - 12:25PM
- An Event-Based Network-on-Chip Monitoring Service
Calin Ciordas, Twan Basten - Eindhoven University of Technology, Andrei Radulescu, Kees Goossens, Jef van Meerbergen - Philips Research Laboratories
- Assertion-Based Power/Performance Analysis of Network Processor Architectures
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang - University of California Riverside, Felice Balarin - Cadence Berkeley Laboratories
- Validation of the dependability of CAN-based networked systems
F. Corno - Politecnico di Torino, J. Perez - Universidad de la Republica Uruguay, M. Ramasso, M. Sonza Reorda, M. Violante - Politechnico di Torino
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Lunch - 12:25PM - 1:45PM
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Session 9 - High Level Validation - 1:45PM - 3:00PM
- High Level Hardware Validation using Hierarchical Message Sequence Charts
Praveen K. Murthy, Sreeranga P. Rajan, Koichiro Takayama - Fujitsu Labs of America
- Analysis of the influence of processor hidden registers on the accuracy of fault injection techniques
D.Gil, J.Gracia, J.C.Baraza, and P. J. Gil - Polytechnic University of Valencia
- On equivalence checking between behavioral and RTL descriptions
Masahiro Fujita - University of Tokyo
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Break - 3:00PM - 3:20PM
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Session 10 - Panel Session - 3:20PM - 5:00PM
- Panel: Driving the Intelligent Testbench: Are We There Yet?
Organizers: Harry Foster - Jasper Design Automation and Prab Varma - Blue Pearl Software
Panelists: - Gary Smith - Gartner Dataquest, - Andrew Piziali - Verisity Design, - Harry Foster - Jasper Design Automation, Jani ck Bergeron - Synopsys, Laurent Fournier - IBM Haifa
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